In recent years, LSI elements configuring semiconductor memory devices are becoming increasingly miniaturized as these semiconductor devices become more highly integrated. Such miniaturization of LSI elements requires not only a simple narrowing of line width, but also improvement in dimensional accuracy and positional accuracy of circuit patterns. Proposed as a technology for overcoming these problems is ReRAM (Resistive RAM) which is configured by memory cells that include a variable resistance element and a selection element such as a diode. A memory cell in this ReRAM does not require the use of a MOSFET and moreover can be configured as a cross-point type. Hence, a high degree of integration exceeding conventional trends is expected of ReRAM.
However, in cross-point type architecture, a half-select bias system is sometimes required. In this half-select bias system, a half-selected cell current flows in addition to an ordinary selected cell current. Hence, when cell size undergoes reduction scaling, voltage drop within the memory cell array does not achieve a simple proportional relationship, and it is thus difficult to keep voltage drop constant.
Furthermore, when employing the half-select bias system, the half-selected cell current also gets mixed in with the selected cell current during data read, thus making read of a selected cell difficult. When reduction scaling of cell size is performed, the proportion of this mixed-in half-selected cell current also increases, leading to problems during miniaturization of semiconductor memory devices.